`timescale 1ns / 1ps

module CLOCK_SYNC(
	input clk_ENC,			// 5MHz
	input rst,				// hold time is much shorter than T_{ENC}
	output rst_sync			// new synced rst signal, which is expected to be alinged with clk_ENC
);

reg[15:0] cnt_enc = 16'd0;
reg rst_sync_sent = 1'b0;

assign rst_sync = (cnt_enc >= 1) && (cnt_enc < 2);

always@( posedge clk_ENC or posedge rst ) begin
	if( rst ) begin
		cnt_enc			<= 16'd0;
		rst_sync_sent	<= 1'b0;

	end
	else begin
		if( rst_sync_sent == 1'b0 ) begin
			if( cnt_enc >= 6 ) begin
				rst_sync_sent <= 1'b1;
			end
			else
				cnt_enc <= cnt_enc + 16'd1;
		end
	end
end


endmodule
